FIGS. 10 and 11A-11C schematically illustrate the configuration of a conventional MOSFET metal-oxide semiconductor field-effect transistor (MOSFET) having trench gate electrodes. FIG. 10 is a plan view of the MOSFET. FIGS. 11A-11C are sectional views taken along lines 11A-1A, 11B-11B, and 11C-11C of FIG. 10. FIGS. 11A-11C, omit the back-side n+ semiconductor substrate on which an n− semiconductor layer 1 is formed, and layers, regions, etc., formed above and on/in the n− semiconductor layer 1. A vertical insulated-gate bipolar transistor (IGBT) can be obtained by replacing the n+ semiconductor substrate with a p+ semiconductor substrate or replacing the n− semiconductor layer 1 with an n− semiconductor substrate and forming a p-type collector layer on its back surface.
A p-well region 10 (p-channel region) is formed (as a surface layer) in the n− semiconductor layer 1. Striped trenches 4 penetrate through the p-well region 10 and reach the n− semiconductor layer 1. Gate insulating films 5 are formed on the surfaces of the trenches 4, and polysilicon gate electrodes 7 are formed in the trenches 4, with the gate insulating films 5 interposed in between. N+ source regions 11 are formed adjacent to the trenches 4 (as surface layers) in the p-well region 10. The n+ source regions 11 are connected to a source electrode 14 through contact holes 13 formed through an interlayer insulating film 12. A terminal portion, which extend along the longitudinal direction of the trench 4, of each gate electrode 7 is connected to a gate polysilicon interconnection 8, which is connected to a gate metal interconnection 15. The gate polysilicon interconnection 8 functions as a field plate. A p-type end region 3 is formed along the chip outer periphery, e.g., circumference. The p-type end region 3 and an end polysilicon film 9 are connected to metal films 16 through contact holes 13 formed through the interlayer insulating film 12.
FIGS. 12A-12B to FIGS. 16A-16C schematically illustrate the method steps, executed in order, of a manufacturing method of the conventional MOSFET having trench gate electrodes of FIGS. 10 and 11A-11C. FIGS. 12A-16A are plan views of the MOSFET. FIGS. 12B-16B are sectional views of the MOSFET taken along lines 12B-12B, 13B-13B, 14B-14B, 15B-15B, and 16B-16B of FIGS. 12A-16A. FIGS. 13C-16C are sectional views of the MOSFET taken along lines 13C-13C, 14C-14C, 15C-15C, 16-C-16C of FIGS. 13A-16A.
Referring to FIGS. 12A and 12B, the p-well region 10 and the p-type end region 3 are formed simultaneously in the n− semiconductor layer 1. Reference symbol a denotes an edge of the p-well region 10. Referring to FIGS. 13A-13C, the striped trenches 4 penetrate through the p-well region 10 and reach the n− semiconductor layer 1. Then, as shown in FIGS. 14A-14C, the surfaces of the trenches 4 are covered with the gate insulating films 5 and filled with a polysilicon material (e.g., film) to form the polysilicon gate electrodes 7. At this time, the polysilicon film is also applied to a thick insulating film 6, which is formed on an end portion of the p-well region 10, an inside end portion of the p-type end region 3, and an exposed portion of the n− semiconductor layer 1 (i.e., an edge breakdown-resistant structure) and patterned into the gate polysilicon interconnection 8 and the end polysilicon film 9.
Subsequently, as shown in FIGS. 15A-15C, n+ source regions 11 are formed adjacent to the trenches 4 (as surface layers) in the p-well region 10. Finally, as shown in FIGS. 16A-16C, an interlayer insulating film 12 and contact holes 13 are formed. A source electrode 14 is formed connected to the n+ source regions 11, a gate metal interconnection 15 is formed connecting to the gate polysilicon interconnection 8, and metal films 16 are formed connecting to the p-type end region 3 and the end polysilicon film 9.
In the vertical MOSFET having trench gate electrodes manufactured in the above-described manner, the channel resistance component is reduced because of the increased channel density due to miniaturization. On the other hand, to reduce the on-resistance, it is also necessary to reduce the resistance component of the drift layer (n− semiconductor layer 1). To this end, the resistivity and the thickness of the drift layer need to be reduced, which deteriorates the breakdown voltage characteristic as long as the conventional edge breakdown-resistant structure is employed.
As mentioned above, the channel resistance component is reduced because of the increased channel density due to miniaturization. But since the p-well region 10 is formed before the gate electrodes 7, the diffusion depth of the p-well region 10 is increased as shown in FIG. 17 due to a heat history (heat treatment) occurring in later steps, such as the step of forming the gate insulating films 5 (gate oxide films). As a result, the channel length increases and the channel resistance component increases accordingly. This partially cancels out the beneficial effect of the miniaturization.
Where the gate insulating films 5 are oxide films, the gate oxide films absorb the impurity from the p-well region 10 and the impurity concentration of the p-well region 10 is lowered in portions close to the side surfaces of the trenches 4, so that the bottom surface of the p-well region 10 becomes curved as shown in FIG. 17. As a result, a J-FET effect (i.e., a phenomenon that junction MOSFETs is formed to increase the on-resistance) occurs near the bottoms of the trenches 4, thereby increasing the on-resistance.
When the diffusion depth of the p-well region 10 is increased, the gate capacitance (gate-drain capacitance) is increased, and the switching speed is thereby lowered, increasing the switching loss. Furthermore, the increase in the diffusion depth of the p-well region 10 makes it necessary to increase the depth of the trenches 4 as shown in FIG. 18, which reduces the breakdown voltage. To prevent this problem, it is necessary to make the n− semiconductor layer 1 thicker. Where the n− semiconductor layer 1 is formed by epitaxial growth, this means cost increase.
U.S. Pat. No. 6,118,150 (Japanese Patent No. 3,410,286), JP-A-8-78668, and JP-A-10-56174 disclose a technique for forming a deep p-type region (corresponds to a RESURF region (described later)) adjacent to the end of an active region (corresponds to the above-described p-well region 10) in a vertical MOS trench gate device. USPGP 2006-54970 (JP-A-2006-80177) discloses a technique for forming a channel layer (corresponds to the above-described p-well region 10) after forming gate oxide films and gate electrodes, to prevent thickening of the p-well region 10 due to the heat history (in forming the gate insulating films 5, the thick insulating film 6, etc.) by forming the trenches 4, the gate insulating films 5, the thick insulating film 6, the gate electrodes 7, and the gate polysilicon interconnection 8 in this order before forming the p-well region 10.
In the above technique, however, as shown in FIGS. 19-21, the gate polysilicon interconnection 8 formed at the same time as the gate electrodes 7 covers the surface portion that extends outward from tip portions of the striped trenches 4. Therefore, the p-well region 10, which is formed at a later step, is not formed around the tip portions of the trenches 4. This means that the end of the p-well region 10 retreats from position a to position b. See FIG. 19, which schematically illustrates a plan view of the MOSFET. FIGS. 20A-20C are sectional views of MOSFET taken along lines 20A-20A, 20B-20B, and 20C-20C of FIG. 19. FIG. 21 is an enlarged view of part E21 of FIG. 19.
As a result, as shown in FIGS. 20B and 21, the side surfaces of the tip portions of the trenches 4 are not surrounded by the p-well region 10 and come into contact with the n− semiconductor layer 1. The degree of electric field concentration is increased there, hence lowering the breakdown voltage. For this reason, it is undesirable to form the gate electrodes 7 and the gate polysilicon interconnection 8 simultaneously before forming the p-well region 10. Moreover, if the diffusion depth of the p-well region 10 is small, the electric field intensity is increased along the edge a, which makes it difficult to attain a high breakdown voltage. The above-described problems will be described below in more detail.
In the method in which the gate electrodes 7 and the gate polysilicon interconnection 8 are formed after forming the p-well region 10 (channel region), the impurity (channel impurity) of the p-well region 10 is absorbed in the later oxidizing step (forming the gate oxide films and the thick oxide film), where the p-well region 10 (channel region) becomes shallow near the side surfaces of the trenches 4 and deep in central portions of the cells that are distant from the trench gate electrodes 7. The on-resistance is increased due to the J-FET effect. In this case, to suppress the J-FET effect, which is caused by the increased diffusion depth of the p-well region 10 (i.e., the depth of the channel diffusion) in the cell central portions, it is necessary to deepen the trench gates (i.e., the gate electrodes 7 in the trenches 4). As a result, the surface areas of the p-well region 10 (channel region) and those portions of the gate electrodes 7 that project from the p-well region 10 are increased, which increases the gate capacitance of the trench 4 part to deteriorate the switching characteristic.
Accordingly, there remains a need for manufacturing a semiconductor device that can reduce the on-resistance while increasing the breakdown voltage, and that can improve the switching characteristic by reducing the gate capacitance. The present invention addresses this need.